1. Field of the Invention
The present invention relates generally to validation of chip designs, and more specifically to application specific integrated circuit (ASIC) validation schemes that reduce the validation time by accelerating test case development without sacrificing quality.
2. Description of the Related Art
Development timelines for integrated circuits (ICs) are constantly being evaluated in order to identify efficiencies for reducing the development timeline in order to make the IC available to the market as fast as possible. At the design stage for an integrated circuit, a circuit design is typically represented as circuit data in a hardware description language (HDL). From the HDL, the circuit design can be mapped (through suitable processing) into an actual hardware design for fabrication in an integrated circuit. Standards exist for HDLs, e.g., Verilog standards.
The testing of circuit designs prior to fabrication in an integrated circuit is referred to in the art as verification and validation, and represents an important step in the design process for an integrated circuit. With the complexity of circuits increasing continuously, it is impossible to guarantee the proper operation of a design without undergoing an extensive prior verification and validation of the design. The HDL-based design methodology requires the user to describe the behavior of a system which may then be simulated (a process referred to as Register Transfer Level (RTL) simulation) to determine whether it will function as desired. The design is then synthesized to create a logical netlist that can be implemented within a particular Programmable Logic Device (PLD) or a particular PLD vendor's device group. Assuming that neither the synthesis or the design implementation processes alter the behavior of the design, RTL simulation provides the designer with insight into the functionality and behavior of the implemented device before the costly and time consuming synthesis and design implementation processes take place. If accurate, RTL simulation represents a quick and efficient means of validating a design's (and ultimately, a programmed device's) behavior.
During the validation process, complete testcases are created as a macrolevel Verilog task. The test cases are compiled along with the testbench and the design. And the simulation is then run. Once the simulation is run it is determined whether the goal of the test case is met. If the goal of the test case is not met, then the RTL is checked. If the RTL check is satisfactory, then the tasks defining the test case are adjusted. It should be appreciated that this process is iterative until the desired tasks for the testcase are determined. At each iteration, the newly defined testcase must be compiled, which consumes CPU resources of the computer system running a commercially available simulation program, e.g., a verilog based simulation program, as well as seat licenses for the simulation program.
As licenses are generally structured to allow a user to perform a compilation or a simulation, and not both at the same time, the user will either have to wait for a license to be available if a simulation is running, or use an additional seat license for the compilation. Thus, an organization will generally have to purchase additional seat licenses to avoid the downtime. Furthermore, the compilations are costly in terms of the design engineer's time and are a bottleneck in the validation process.
Another shortcoming of the current validation process is that the initialization of the chip model may require 30 minutes or more. Thus, for each test case a thirty minute initialization process is incurred. Accordingly, as test cases are developed and modified throughout the validation and verification schemes, the thirty minute initialization periods begin to add up to a significant amount of time. The design engineer is basically idle during the wait period for the initialization, thereby resulting in the inefficient use of his/her time. In addition, a seat license for the software associated with the validation process is consumed during this inactive initialization period.
In light of the foregoing, it is desired to implement a scheme to reduce the initialization time for the chip model during test case development in order to more efficiently perform the validation of a design of an integrated circuit.